With continuous developments of microelectronic technology, III-V group compound semiconductors, such as InGaAs, InP, InAs, GaAs, GaSb, etc., are superior to silicon in terms of electron mobility or hole mobility, so they are considered to be an important alternative to replace metal for manufacturing silicon channel of metal-oxide-semiconductor field effect transistor (MOSFET) in more-Moore ages.
There are plenty of interfacial trap densities at interfaces of Group III-V substrate and a gate dielectric, which is generally at 1-2 orders of magnitude higher than that of an interface of SiO2/Si. The higher interfacial trap density will greatly decrease the carrier mobility, which leads to an increased on-resistance and increased power consumption. At present, the interface quality and overall properties of the gate dielectric/Group III-V substrate have been improved by the researcher utilizing methods such as Al2O3 surface passivation, interface sulfur treatment and surface nitridation on the basis of atomic layer deposition technology. However, it is still poorer as compared with the SiO2/Si interface quality.
In addition, from the viewpoint of reliability and power consumption of the device, it provides many challenges for the Group III-V substrate and gate dielectric structure. Most of the current gate dielectric structure has disadvantages of large leakage current of the gate dielectric and poor reliability. It is a critical technical about how to fabricate gate dielectrics with high reliability, low defect interface state density and ultra-low equivalent oxide thickness on the surface of the Group III-V substrate so as to apply Group III-V substrate in logic devices in the post-mole technology era.